Recently, in the field of LSIs (Large Scale Integrated circuits) for wireless communication to which a fine CMOS (Complementary MOS (Metal-Oxide-Semiconductor)) process is applied, the degree of integration has been increased. In conventional LSIs for wireless communication, an analog PLL circuit is usually employed as a PLL (Phase Locked Loop) circuit.
In the case of an analog PLL circuit, phase difference information is produced by a phase comparator (PD) as a pulse width, and electrical charge that is produced by a charging pump circuit (CP) according to the pulse width is converted into voltage information by a loop filter. Oscillating frequency is controlled by supplying the voltage information from the loop filter into a control voltage terminal of a VCO (Voltage Controlled Oscillator). Such an analog PLL cannot gain such benefits as size reduction or cost reduction as a result of miniaturization of the circuit because it uses elements such as resistances and capacitances in its loop filter or the like. Moreover, the voltage is lowered by the miniaturization, which poses a problem of deterioration in characteristics due to source noise or the like.
In recent years, on the other hand, researches and developments of fully digital PLL circuits have been conducted for configuring the PLL circuits in digital fashion. In a fully digital PLL circuit, frequency is controlled by digitally switching a micro varactor in order to control a VCO. Therefore, instead of a phase comparator producing phase difference information as a pulse width used by a conventional analog PLL, a digital phase comparator is required which produces phase difference information as a digital value.
One of known configurations of such digital phase comparators is shown in FIG. 1 (Patent Document 1: JP 2002-076886A). FIG. 2 is a timing chart for explaining operation of the circuit of FIG. 1. An output signal CLK1 of a VCO is sequentially delayed by a cascade-connected inverter array, and output signals of respective inverters of the inverter array are latched by flip-flops using a reference clock signal CLK2 as a clock, whereby a digital phase comparator is realized, which produces a phase difference as a digital value. When the output signals of the respective inverters of the inverter array are sampled at the rising edge of the reference clock signal CLK2, comparison results of QC(1) to QC(8) (QC(1:8) in FIG. 2) are obtained. A logic circuit detects a logic change of QC(1) to QC(8) to produce a digital code.
Another known configuration of a digital phase comparator is shown in FIG. 3 (Patent Document 2: JP 2007-110370A). According to the configuration of FIG. 3, not only an output signal CLK1 from a VCO is sequentially delayed by a first inverter array, but also a reference clock signal CLK2 is sequentially delayed by a second inverter array, and these signals are latched by flip-flops. Outputs DF(1), DF(2), . . . DF(n) from the respective inverters of the first inverter array are sampled with the flip-flops by using the edges of outputs CKF(1), CKF(2), . . . CKF(n) from the respective inverters of the second inverter array (using the rising edges for odd-numbered inverters such as first and third inverters, and using the falling edges for even-numbered inverters such as second and fourth inverters), whereby QF(1), QF(2), . . . QF(n) are produced. As shown in a timing chart of FIG. 4, phase comparison is conducted in terms of resolution of delay time difference between the first inverter array and the second inverter array. A logic circuit detects a logic change of QF(1) to QF(8) (the logic change of QF(1) to QF(3) is zero, and the logic change of QF(4) to QF(8) is one), and produces a digital code.